Programmable Logic Users Group Mini PL-UG Fest 2008

Jim Lumia jlumia@ieee.org	Tuesday, November 11, 2008 at 9:00 AM
	Meeting Description November Chapter Event AESS, Computer Society, and PL-UG Programmable Logic Users Group’s Mini PL-UG Fest 2008 Date/Time: Tuesday, November 11, 2008, 9:00 AM to 4:00 PM Holiday Inn Select 3535 Ulmerton Road Clearwater, FL 33762 This event sponsored is by the Florida West Coast Aerospace & Electronic Systems Society (AESS) and the Programmable Logic Users Group (PL-UG). This Mini PL-UG Fest will feature Xilinx programmable logic technology and embedded systems design with an emphasis on FPGA technology. Other vendors will have equal opportunity to participate in Mini PL-UG Fests in 2009. This is an open meeting and there is no charge for attendees. Non-members and students are welcome. Lunch will provided by Xilinx. On Tuesday, November 11th, PL-UG Fest offers free admission and lunch. Please register prior to the event to reserve your lunch. Lunch will be provided to the first 45 reservations. Presentations begin at 9:00AM and the day ends at 4:00PM. The event will feature application-oriented presentations and demonstrations from Xilinx. Topics include industry outlook and future FPGA products, as well as other embedded processing guidance from Xilinx application engineers. Agenda 9 :00 AM Xilinx ISE Tools Tips and Tricks This course demonstrates several tools tips and shortcuts that can be used to speed development and achieve timing closure on designs. Covers version 10.1.03i of the Xilinx tools 10:00 AM Accurate Power Estimation using Xilinx Power Estimation tool This course covers how to use the XPE tool to generate accurate power estimates of Xilinx designs early in the design cycle. 11:00 AM Achieving Breakthrough Performance with the New PowerPC 440 Processor Architecture This course covers the differences between the PowerPC405 architecture of the Virtex4 FPGA’s and the new PowerPC 440 of the new V5 FXT devices and this dramatically improves the performance of processor based designs. 12:00 PM Xilinx Next Generation Product Roadmap This lunch topic highlights the next generation products from Xilinx from both the high performance and high volume product lines. 1:00 PM GTX/GTP Wizard for High Speed Serial I/O designs Learn how to quickly create High Speed Serial I/O designs for Virtex-5 devices. The Wizard allows the user to configure one or more GTX/GTP tiles by choosing one of the industry standard protocols as a template. Resulting source code design can then be customized as needed or implemented ‘as is’. Session will include steps to simulate the design and a 6.5 Gbps demo in hardware. 2:00 PM Designing for Low Power This course covers design techniques that can be used to reduce dynamic power consumption of designs. These power reduction techniques can be applied to any Xilinx product family. 3:00 PM Introduction to the Spartan-3A DSP Video Starter Kit The Course covers the architecture of the board and how to use System Generator to develop designs that can be run on the Video Starter Kit. Example designs are used to show the development process complete from camera interface to display. Door prizes from Xilinx! You must be present to win. Please RSVP online on this page. Select "Make a Reservation", then "View Attendees List" to check your reservation. Companies wishing to participate in other 2009 Mini PL-UG Fests can call Jim Lumia at 813-832-3501 or JLumia@ieee.org
	Additional Information This is a Joint Meeting with the Programmable Logic Users Group (www.pl-ug.org). If you have problems registering on this web site, please email your registration information to JLumia@ieee.org.
	Meeting Location Holiday Inn Select 3535 Ulmerton Road, Clearwater Driving Directions Click on Mapquest above.
	This reservation service is provided by Time2Meet.com.